SEN2201 · Week 3 · Digital Logic Structures (logic gates, combinational logic circuits)

Transistors, logic gates and Boolean algebra

From the MOS transistor to CMOS gates, from the truth table to the SOP expression, minterms/maxterms and simplification with Boolean algebra. Circuit reading and simplification questions come from here.

MOS transistorn-typep-typeCMOSlogic gateNANDNORXORtruth tablesum of products (SOP)mintermmaxtermDeMorgan's lawlogical completenessBoolean algebra

The bottom floor of a computer is the transistor. Gates are built from transistors, circuits from gates. On this page you see the two lowest levels (devices and logic circuits). The question types from this part on the midterm are well known: read a circuit diagram and produce the truth table, write an expression from a table, simplify an expression with Boolean algebra, take its complement with DeMorgan, write it using only NAND.

The MOS transistor

A MOS transistor is an electrical switch. It has three terminals: gate, source and drain. The voltage applied to the gate decides whether current passes between the other two terminals.

TypeGate = 1 (high voltage)Gate = 0
n-typeconducts (closed switch)does not conduct (open circuit)
p-typedoes not conductconducts

In CMOS (complementary MOS) circuits both types are used together in every gate. The p-types connect the output to +V (logical 1), the n-types to GND (logical 0). In a correctly designed CMOS gate, for every input exactly one of these two paths is open.

CMOS NOT, NAND, NOR

NOT (inverter): one p, one n. Input 0 → p conducts → output 1. Input 1 → n conducts → output 0.

NAND: the p-types are in parallel (between +V and the output), the n-types are in series (between the output and GND). For the output to be 0, the whole series path must conduct, that is A = B = 1. In every other case one of the parallel p’s pulls the output to 1.

NOR: the exact opposite. The p-types are in series, the n-types in parallel. The output is 1 only when A = B = 0.

AND and OR gates are not built directly in CMOS. AND = NAND + NOT, OR = NOR + NOT. That is why the “cheapest” gates in circuits are NAND and NOR.

TIP · Series = AND, parallel = OR. With switches in series, all of them must be closed for current to pass (AND). In parallel, one is enough (OR). Since the n-types of a NAND are in series, it says “if A AND B, connect to GND”.

Logic gates

ABANDORNANDNORXORXNOR
00001101
01011010
10011010
11110001

In diagrams: the D shape with a flat back is AND, the curved-back shape with a pointed tip is OR, anything with a small circle (bubble) at its tip is the complement of that gate (NAND, NOR), and a triangle ending in a circle is NOT. XOR carries a second curve behind the OR shape.

Notation: A′A' (or A‾\overline{A}) = NOT A, writing side by side ABAB = AND, ++ = OR, ⊕\oplus = XOR. Order of operations: NOT > AND > OR.

Truth table → expression

Minterm and SOP

The table of a function with nn inputs has 2n2^n rows. The rows are numbered from 0 to 2n−12^n - 1 (ABC = 101 → row 5).

A minterm is the AND term that is 1 in a single row. The rule: if the bit is 1 the letter itself, if the bit is 0 its complement. m5=AB′Cm_5 = AB'C.

The canonical SOP (sum of products) form of a function: write the minterm of every row where F = 1 and OR them all. The short notation is Σm(…)\Sigma m(\ldots).

A B C | F
0 0 0 | 1   ← m0 = A'B'C'
0 0 1 | 1   ← m1 = A'B'C
0 1 0 | 0
0 1 1 | 0
1 0 0 | 0
1 0 1 | 1   ← m5 = AB'C
1 1 0 | 0
1 1 1 | 0

F = Σm(0,1,5) = A'B'C' + A'B'C + AB'C

This expression turns directly into a circuit: one AND gate for each term, a single OR gate at the end. This means: every truth table can be built with AND, OR and NOT. This property is called logical completeness.

Maxterm and ΠM

A maxterm is the OR term that is 0 in a single row. The rule is the opposite of the minterm: bit 0 → the letter itself, bit 1 → its complement. M5=(A′+B+C′)M_5 = (A' + B + C').

F=Σm(rows with F=1)=ΠM(rows with F=0)F′=Σm(rows with F=0)F = \Sigma m(\text{rows with F}=1) = \Pi M(\text{rows with F}=0) \qquad F' = \Sigma m(\text{rows with F}=0)

In the example above, F=ΠM(2,3,4,6,7)F = \Pi M(2,3,4,6,7) and F′=Σm(2,3,4,6,7)F' = \Sigma m(2,3,4,6,7).

PITFALL · mixing up the letter rule of minterms and maxterms. m5 = 101 → AB′CAB'C (plain if 1). M5 = 101 → (A′+B+C′)(A' + B + C') (complemented if 1). The opposite operation, the opposite rule.

Boolean algebra

RuleOR formAND form
IdentityX+0=XX + 0 = XX⋅1=XX \cdot 1 = X
NullX+1=1X + 1 = 1X⋅0=0X \cdot 0 = 0
IdempotentX+X=XX + X = XX⋅X=XX \cdot X = X
ComplementX+X′=1X + X' = 1X⋅X′=0X \cdot X' = 0
Involution(X′)′=X(X')' = X
DistributiveX+YZ=(X+Y)(X+Z)X + YZ = (X+Y)(X+Z)X(Y+Z)=XY+XZX(Y+Z) = XY + XZ
AbsorptionX+XY=XX + XY = XX(X+Y)=XX(X+Y) = X
CombiningXY+XY′=XXY + XY' = X
DeMorgan(X+Y)′=X′Y′(X + Y)' = X'Y'(XY)′=X′+Y′(XY)' = X' + Y'
ConsensusXY+X′Z+YZ=XY+X′ZXY + X'Z + YZ = XY + X'Z

One more that is used a lot: X+X′Y=X+YX + X'Y = X + Y.

Simplification recipe

  1. Find two minterms that differ in only one variable.
  2. Factor out the common factor: AB′C′+AB′C=AB′(C′+C)AB'C' + AB'C = AB'(C' + C).
  3. C′+C=1C' + C = 1, leaving AB′AB'.
  4. If you need to use a term in two pairings, copy it first (X=X+XX = X + X).
  5. Check the result against the table: which rows does each term cover?

Worked example: the F=A′B′C′+A′B′C+AB′CF = A'B'C' + A'B'C + AB'C above.

F = A'B'C' + A'B'C + AB'C
  = A'B'C' + A'B'C + A'B'C + AB'C      idempotent: A'B'C was copied
  = A'B'(C' + C) + B'C(A' + A)         distributive
  = A'B'·1 + B'C·1                     complement
  = A'B' + B'C                         identity
check: A'B' → 000, 001 (m0, m1) · B'C → 001, 101 (m1, m5) ✓

Taking the complement with DeMorgan

If F=A′B′+B′CF = A'B' + B'C:

F' = (A'B' + B'C)'
   = (A'B')' · (B'C)'          DeMorgan (complement of a sum)
   = (A + B) · (B + C')        DeMorgan (complement of a product), involution
   = AB + AC' + BB + BC'       distributive
   = AB + AC' + B + BC'        idempotent BB = B
   = B + AC'                   absorption: B + AB = B, B + BC' = B

Check: the rows where F′F' = 1: B = 1 (2, 3, 6, 7) and AC’ (4, 6). The union is {2, 3, 4, 6, 7}. Combined with the set {0, 1, 5} of F it gives {0..7}, with no common element.

Circuit reading

In the exam a diagram is given and you are asked: recognize each gate, name the intermediate outputs, fill in the table, write the expression, simplify, answer the “which operation?” question.

Example: Gate 1 is a NOR (inputs A, B), its output is X. Gate 2 is an AND (inputs B, C), its output is Y. Gate 3 is an OR (inputs X, Y), its output is F.

A B C | X=(A+B)' | Y=BC | F=X+Y
0 0 0 |    1     |  0   |  1
0 0 1 |    1     |  0   |  1
0 1 0 |    0     |  0   |  0
0 1 1 |    0     |  1   |  1
1 0 0 |    0     |  0   |  0
1 0 1 |    0     |  0   |  0
1 1 0 |    0     |  0   |  0
1 1 1 |    0     |  1   |  1

F = (A+B)' + BC = A'B' + BC = Σm(0, 1, 3, 7)

Recognize the patterns: A′B+AB′A'B + AB' is XOR, A′B′+ABA'B' + AB is XNOR, S′A+SBS'A + SB is a 2-to-1 mux, AB+AC+BCAB + AC + BC is majority.

Using only NAND (or NOR)

NAND alone is complete (logically complete): AND, OR and NOT can all be written with NAND.

WantedWith NAND
A′A'NAND(A, A)
ABABNAND(NAND(A,B), NAND(A,B))
A+BA + BNAND(NAND(A,A), NAND(B,B))
AB+CDAB + CDNAND(NAND(A,B), NAND(C,D))

Recipe: write the SOP expression, complement it twice, apply DeMorgan to the inner one.

F=AB+CD=((AB+CD)′)′=((AB)′⋅(CD)′)′F = AB + CD = ((AB + CD)')' = ((AB)' \cdot (CD)')'

Result: make every gate in the AND-OR circuit a NAND, and the circuit stays the same. For NOR the same idea works with the POS (product of sums) expression.

Common mistakes

Wrong ideaThe truth
An n-type conducts at gate = 0An n-type at gate = 1, a p-type at gate = 0
In a NAND the n-types are in parallelIn a NAND n is in series, p in parallel
(AB)′=A′B′(AB)' = A'B'(AB)′=A′+B′(AB)' = A' + B'
(A+B)′=A′+B′(A+B)' = A' + B'(A+B)′=A′B′(A+B)' = A'B'
m5 = A′BC′A'BC'm5 = 101 = AB′CAB'C
The ΠM list = the Σm listΠM is the rows where F = 0
A+AB=A+BA + AB = A + BA+AB=AA + AB = A; A+A′B=A+BA + A'B = A + B
I cannot use a term twiceX=X+XX = X + X, you can copy it

Test yourself

Exam-style questions. Solve them on paper first, then reveal the answer.

Question 1easy

When does an n-type MOS transistor conduct? When does a p-type conduct?

Show answer
n-type: gate = 1; p-type: gate = 0

When a 1 (high voltage) arrives at the gate of an n-type transistor, the channel forms and it conducts, behaving like a closed switch. The p-type is the opposite: it conducts when the gate is 0. In CMOS the p-types connect the output to +V (1) and the n-types to GND (0).

Question 2medium

In a 2-input CMOS NAND gate, how are the p-type and n-type transistors connected?

Show answer
p-type in parallel (to +V), n-type in series (to GND)

The output of a NAND must be 0 only when both inputs are 1. So the path to GND is built with two n-types in series: both must conduct. If any input is 0, one of the parallel p-types connects the output to +V. In a NOR it is the opposite: the p-types are in series, the n-types in parallel.

Question 3easy

How many rows does the truth table of a 4-input Boolean function have?

Show answer
16

Each input is 0 or 1. For nn inputs there are 2n2^n combinations: 24=162^4 = 16 rows.

Question 4easy

F(A,B,C) = Σm(1, 4, 7). Write the canonical sum-of-products expression.

Show answer
A'B'C + AB'C' + ABC

Convert the number of each minterm to binary; if the bit is 1 use the letter itself, if 0 its complement: m1 = 001 → A'B'C, m4 = 100 → AB'C', m7 = 111 → ABC. OR them all.

Question 5medium

Simplify F = AB + AB' + A'B using Boolean algebra.

Show answer
A + B

AB + AB' = A(B + B') = A·1 = A (distributive, complement, identity). F = A + A'B.
A + A'B = (A + A')(A + B) = A + B (distributive). Check with the table: only the 00 row is 0, so it is an OR.

Question 6medium

F(A,B,C) = Σm(1, 3, 5, 6). Simplify F to a sum of products with 3 terms.

Show answer
A'C + B'C + ABC'

Pair them up: m1 (001) and m3 (011) differ only in B → A'C. m1 (001) and m5 (101) differ only in A → B'C (using m1 twice is allowed, X = X + X). m6 (110) stays alone because none of its neighbors is 1: ABC'.
F = A'C + B'C + ABC'. It cannot be written with fewer terms (checked by brute force).

Question 7medium

Using DeMorgan's laws, find the complement of F = AB + C'.

Show answer
(A' + B')C

F′=(AB+C′)′=(AB)′⋅(C′)′=(A′+B′)⋅CF' = (AB + C')' = (AB)' \cdot (C')' = (A' + B') \cdot C. Check: F' is 1 only in m1, m3, m5, F is 1 in the remaining 5 rows; the union is {0..7}.

Question 8easy

F(A,B,C) = Σm(0, 2, 5, 7). Write F in product-of-maxterms form ΠM(…).

Show answer
ΠM(1, 3, 4, 6)

The rows where F = 0 form the maxterm list: {0..7} - {0, 2, 5, 7} = {1, 3, 4, 6}. No calculation, just the ones not in the list.

Question 9medium

Write the maxterm M5 for a 3-variable function F(A,B,C).

Show answer
(A' + B + C')

5 = 101. The maxterm rule is the opposite of the minterm: bit 0 → the letter itself, bit 1 → its complement. A = 1 → A', B = 0 → B, C = 1 → C'. M5 is 0 only when ABC = 101.

Question 10medium

Implement F = AB + CD using only NAND gates. Write the expression.

Show answer
NAND(NAND(A,B), NAND(C,D))

With a double complement: F=((AB+CD)′)′F = ((AB + CD)')'. DeMorgan on the inside: (AB+CD)′=(AB)′(CD)′(AB+CD)' = (AB)'(CD)'. So F=((AB)′(CD)′)′F = ((AB)'(CD)')' = NAND(NAND(A,B), NAND(C,D)). A two-level AND-OR circuit becomes a two-level NAND-NAND circuit exactly.

Question 11hard

A circuit computes X = NAND(A,B), Y = NAND(A,X), Z = NAND(B,X), F = NAND(Y,Z). Which basic operation is F?

Show answer
XOR

Make the table (A B → X Y Z F): 00 → 1 1 1 0; 01 → 1 1 0 1; 10 → 1 0 1 1; 11 → 0 1 1 0.
F = 0110 = A ⊕ B. The classic XOR circuit built with four NANDs.

Question 12hard

F(A,B,C) = Σm(0, 1, 2, 4). Give a simplified sum of products.

Show answer
A'B' + A'C' + B'C'

m0 (000) is a neighbor of all three other minterms. Pair them: m0+m1 → A'B', m0+m2 → A'C', m0+m4 → B'C'.
F = A'B' + A'C' + B'C'. That is, F = 1 when at most one input is 1 (the complement of the majority function).

Verification: Every gate table, every simplification and every minterm/maxterm list was verified with node by trying all input combinations (exhaustive truth table); the minimum number of terms was checked by brute force (verify/SEN2201/03.mjs).

Review card

n-MOS: conducts when gate=1 (GND side) | p-MOS: conducts when gate=0 (+V side) CMOS NOT: 1p+1n | NAND: p parallel, n series | NOR: p series, n parallel AND 0001 OR 0111 NAND 1110 NOR 1000 XOR 0110 XNOR 1001 (inputs 00,01,10,11) n inputs -> 2^n rows minterm: 1 -> plain, 0 -> complemented (m5=AB'C) | maxterm: 0 -> plain, 1 -> complemented (M5=A'+B+C') F = Σm(F=1) = ΠM(F=0) | F' = Σm(F=0) SOP: AND the 1 rows, OR them X+X'=1 XX'=0 X+XY=X X+X'Y=X+Y XY+XY'=X DeMorgan: (XY)'=X'+Y' (X+Y)'=X'Y' Consensus: XY + X'Z + YZ = XY + X'Z NAND-only: AND-OR -> NAND-NAND, X' = NAND(X,X) {AND,OR,NOT} is complete; NAND alone is complete; NOR alone is complete Precedence: NOT > AND > OR