The von Neumann model and the instruction cycle
The five parts of a computer, the jobs of PC/IR/MAR/MDR and the six phases of an instruction (FETCH, DECODE, EVALUATE ADDRESS, FETCH OPERANDS, EXECUTE, STORE RESULT). With LC-3 examples.
In the first four weeks you saw the parts: gates, adder, mux, register, memory. This week we put them together and make a computer. The model described by John von Neumann in 1946 is still the basis of every processor today. On this page you will learn the five parts of the model and how an instruction is processed (the instruction cycle). In the examples we use LC-3 instructions; the details of the instructions come in weeks 7-8.
On the midterm, this topic usually brings short-answer questions: list the five parts, what PC/IR/MAR/MDR hold, order the six phases, write the FETCH steps, what happens after FETCH if PC = x3000.
The von Neumann model
+-------------------------------+
| MEMORY |
| MAR MDR |
+-------------------------------+
^ ^
| |
INPUT ---> +------------------------+ ---> OUTPUT
(keyboard) | PROCESSING UNIT | (screen)
| ALU TEMP (R0-R7)|
+------------------------+
^
|
+------------------------+
| CONTROL UNIT |
| PC IR |
+------------------------+| Part | Job | In the LC-3 |
|---|---|---|
| Memory | Stores the program and data | locations × 16 bits, MAR and MDR |
| Processing unit | Does the calculation | ALU (ADD, AND, NOT), R0-R7 |
| Input | Takes data from the outside world | Keyboard |
| Output | Gives data to the outside world | Screen (monitor) |
| Control unit | Manages which step is done | PC, IR, the control FSM |
Memory: MAR and MDR
These two registers are the only way to access memory.
- Read: write the address into the MAR, and memory puts the contents of that location into the MDR.
- Write: write the address into the MAR and the value into the MDR, and give the write signal (WE).
Processing unit
It consists of the ALU (arithmetic and logic unit), which does the operations, and small, fast registers that hold intermediate results. Going to memory is slow; that is why frequently used values are kept in registers. The LC-3 has 8 of them: R0-R7. The number of bits the ALU processes at a time is called the word length (LC-3: 16 bits).
Control unit: PC and IR
- PC (program counter): the address of the next instruction. Its name says “counter”, but it is really a pointer.
- IR (instruction register): the instruction currently being processed, itself.
The control unit is an FSM (week 4). It decides which signals to turn on in each clock cycle.
The stored-program concept
The program’s instructions also sit in memory as bits, like any data. The computer is not rewired for a new job; a new program is loaded into memory. This is called the stored-program concept and is the essence of the von Neumann model.
PITFALL · confusing the PC with the IR. The PC holds an address (like x3001), the IR holds an instruction (like x1263). Writing “the PC holds the current instruction” is a classic mistake: after FETCH the PC is already pointing to the next one.
The instruction
An instruction consists of two parts: the opcode (what to do) and the operands (what to do it with). In the LC-3 every instruction is 16 bits, and the opcode is the top 4 bits (IR[15:12]).
x1263 = 0001 001 001 1 00011
ADD R1 R1 imm #3 → ADD R1, R1, #3 (R1 ← R1 + 3)The instruction cycle
For every instruction, the computer goes through the same six phases in order, then moves on to the next instruction. Without stopping, until HALT.
| # | Phase | What happens? |
|---|---|---|
| 1 | FETCH | The instruction is brought from memory to the IR, the PC is incremented |
| 2 | DECODE | The opcode is decoded: which instruction, where are the operands? |
| 3 | EVALUATE ADDRESS | If a memory access is needed, the address is computed |
| 4 | FETCH OPERANDS | The operands are taken from registers or memory |
| 5 | EXECUTE | The operation is done (the ALU adds, ANDs…) |
| 6 | STORE RESULT | The result is written to its destination (register or memory) |
FETCH in detail
1. MAR ← PC (send the address to memory)
PC ← PC + 1 (the PC is incremented in the same cycle)
2. MDR ← M[MAR] (memory is read, may take several cycles)
3. IR ← MDR (the instruction is in the IR)If you start with PC = x3000, when FETCH is over PC = x3001, IR = M[x3000]. The PC is incremented before the instruction runs. This detail will be very important in week 7 in PC-relative address calculation: the offset is added to the incremented PC.
DECODE
IR[15:12] enters a 4-to-16 decoder. Exactly one output of the decoder becomes 1: the instruction is determined. The remaining 12 bits are interpreted as different fields depending on the instruction.
Not every instruction uses every phase
| Instruction | EVALUATE ADDRESS | FETCH OPERANDS | EXECUTE | STORE RESULT |
|---|---|---|---|---|
ADD R1, R2, R3 | none | R2, R3 are read | the ALU adds | R1 ← result |
LDR R4, R2, #-3 | R2 + (-3) | MDR ← M[address] | none | R4 ← MDR |
LD R1, LABEL | PC + offset | MDR ← M[address] | none | R1 ← MDR |
ST R1, LABEL | PC + offset | R1 is read | none | M[address] ← R1 |
BRz LABEL | PC + offset | none | if Z = 1 then PC ← address | none |
Worked example
At address x3000 in memory there is LDR R4, R2, #-3, R2 = x4005 and M[x4002] = x00AB.
FETCH MAR ← x3000, PC ← x3001, MDR ← M[x3000], IR ← MDR
DECODE opcode 0110 = LDR, DR = R4, BaseR = R2, offset6 = -3
EVALUATE ADDRESS x4005 + (-3) = x4002
FETCH OPERANDS MAR ← x4002, MDR ← M[x4002] = x00AB
EXECUTE (none)
STORE RESULT R4 ← x00AB, condition code: P (positive)
result: R4 = x00AB, PC = x3001This instruction went to memory twice: once to fetch the instruction, once to read the data. ADD goes once (only the FETCH), LDI three times (instruction, address, data).
Changing the sequential flow
Normally every FETCH increments the PC by one; the program advances line by line. Control instructions change this flow. For example, the BRz instruction writes a new address into the PC in the EXECUTE phase if the last value written was zero. The next FETCH starts from there. Loops and ifs are built this way (week 8).
Clock and HALT
The control unit works with clock cycles. An instruction takes several cycles (memory access is usually the slowest part). If the clock stops, the computer stops. In the LC-3, the HALT (TRAP x25) instruction shuts off the clock signal by calling a routine of the operating system.
Common mistakes
| Wrong idea | The truth |
|---|---|
| The PC holds the current instruction | The PC is the address of the next instruction; the instruction is in the IR |
| The PC is incremented after the instruction finishes | In FETCH, before the instruction runs |
| The MAR holds the data | MAR is the address, MDR is the data |
| Every instruction uses all six phases | ADD has no EVALUATE ADDRESS, LD has no EXECUTE |
| Phases: FETCH, EXECUTE, DECODE … | FETCH, DECODE, EVALUATE ADDRESS, FETCH OPERANDS, EXECUTE, STORE RESULT |
| The program and the data are in separate memories | Stored program: the same memory |
| x30FF + 1 = x3000 | x3100 |
| A branch happens in FETCH | The PC is changed in EXECUTE |
Test yourself
Exam-style questions. Solve them on paper first, then reveal the answer.
Name the five components of the von Neumann model.
Show answer
Memory (with MAR and MDR), processing unit (ALU and temporary registers), input (keyboard), output (screen) and control unit (PC and IR). The program and the data sit in the same memory.
What does the program counter (PC) contain? What does the instruction register (IR) contain?
Show answer
The PC holds an address: the place in memory of the next instruction. The IR holds the instruction itself (the 16-bit machine code). The name PC is misleading; it is not a counter but a pointer (instruction pointer).
Which register holds the address for a memory access, and which holds the data being read or written?
Show answer
To read memory, the address is written into the MAR (memory address register), and memory puts the value read into the MDR (memory data register). To write, the address is put in the MAR, the data in the MDR, and the write signal is given.
List the six phases of the instruction cycle in order.
Show answer
Every instruction follows this order. But not every instruction uses every phase: ADD does not compute a memory address, and the EXECUTE phase of LD is empty.
Write the register transfers of the FETCH phase.
Show answer
First the address in the PC goes to the MAR, and at the same time the PC is incremented by one. Memory is read, and the instruction arrives in the MDR. In the last step the instruction in the MDR is copied to the IR. The PC is incremented BEFORE the instruction runs.
Before the FETCH phase, PC = x30FF. What is the PC after FETCH?
Show answer
During FETCH, PC ← PC + 1. x30FF + 1 = x3100 (in hex F + 1 = 10, the carry goes left). The PC is incremented first whatever the instruction is; a branch instruction can change it later in EXECUTE.
Which phase does ADD R1, R2, R3 not need?
Show answer
The operands of ADD are in registers. No memory address is computed. In FETCH OPERANDS R2 and R3 are read, in EXECUTE the ALU adds, and in STORE RESULT the result is written to R1.
LDR R4, R2, #-3 is executed with R2 = x4005. What address is computed in the EVALUATE ADDRESS phase, and in which phase is memory read?
Show answer
EVALUATE ADDRESS: R2 + (-3) = x4005 - 3 = x4002. FETCH OPERANDS: MAR ← x4002, MDR ← M[x4002]. STORE RESULT: R4 ← MDR. The EXECUTE phase is empty in this instruction.
What is meant by the stored-program concept?
Show answer
In the von Neumann model the program is data too: instructions sit in memory as bits and are read like data. The computer is not rewired for a new job; a new program is loaded into memory.
How does a branch instruction change the sequential flow of a program, and in which phase?
Show answer
Normally FETCH increments the PC by one and the program moves on to the next instruction. A branch (BR, JMP) writes a new address into the PC in the EXECUTE phase. The next FETCH starts from this address.
How many memory accesses (including the instruction fetch) does each LC-3 instruction need: ADD, LDR, LDI?
Show answer
ADD: only the FETCH (reading the instruction). LDR: FETCH + reading the data = 2. LDI: FETCH + reading the address from memory + reading the data at that address = 3. That is why LDI is slower.
In the LC-3, how wide are the MAR and the MDR? Explain why.
Show answer
The MAR holds an address: the LC-3's address space is , so the address is 16 bits. The MDR holds the contents of a memory location: the addressability is 16 bits. They are 16 bits for different reasons; on another machine they could differ (for example a 32-bit address, 8-bit addressability).
Verification: The PC increment, the address calculations and the number of memory accesses of each instruction were measured by running instruction by instruction on an LC-3 simulator we wrote ourselves (verify/SEN2201/lc3.mjs) (verify/SEN2201/05.mjs).